In recent years, a phase-change memory has been developed (e.g., refer to PTL 1). A phase-change memory stores information by changing and recording the resistance of an information memory element of a memory cell.
This is caused by a mechanism in which, when an electric current is caused to flow between a bit line and a source line by turning ON a cell transistor, heat is generated by a high-resistance element serving as a heater, chalcogenide glass (GST: Ge2Sb2Te5) that is in contact with the heater is melted, and a state transition occurs. When chalcogenide glass is melted at high temperature (high current) and cooled rapidly (the application of an electric current is stopped), the chalcogenide glass is brought into an amorphous state (reset operation). When chalcogenide glass is melted at relatively-low high temperature (low current) and cooled slowly (the amount of an electric current is gradually decreased), the chalcogenide glass is crystallized (set operation). Thus, in the readout, information of “0” or information of “1” is determined in accordance with the case where the amount of an electric current that flows between the bit line and the source line is large (low resistance, that is, crystalline state) or the case where the amount is small (high resistance, that is, amorphous state) (e.g., refer to PTL 1).
In this case, the reset current is very high, namely, 200 μA. To cause such a high reset current to flow through the cell transistor, the size of a memory cell needs to be considerably large. To cause a high current to flow, a selection element such as a bipolar transistor or a diode can be used (e.g., refer to PTL 1).
Diodes are two-terminal elements. Therefore, in the selection of memory cells, if a single source line is selected, electric currents of all memory cells connected to the single source line flow through the single source line. As a result, the IR drop increases due to the resistance of the source line.
Bipolar transistors are three-terminal elements. In bipolar transistors, an electric current flows through a gate and thus it is difficult to connect many transistors to word lines.
When the cross-sectional areas of a GST film and a heater element in a current-flowing direction are decreased, the reset current and the read current can be decreased. The cross-sectional areas of a GST film and a heater element in a current-flowing direction have been conventionally decreased by forming a heater element on a side wall of a gate of a planar transistor and forming a GST film in an upper portion of the gate. In this method, a cell string constituted by planar transistors is required (e.g., refer to PTL 1).
A surrounding gate transistor (hereafter referred to as “SGT”) having a structure in which a source, a gate, and a drain are arranged vertically with respect to a substrate and a gate electrode surrounds a pillar-shaped semiconductor layer has been proposed (e.g., refer to PTL 2). Since a source, a gate, and a drain are arranged vertically with respect to a substrate, a small cell area can be realized.
In known MOS transistors, a metal gate-last process in which a metal gate is formed after a high-temperature process has been employed in actual products in order to perform both a metal gate process and a high-temperature process (e.g., refer to NPL 1). A polysilicon gate is formed, an interlayer insulating film is deposited, the polysilicon gate is exposed by performing chemical mechanical polishing, the polysilicon gate is etched, and then a metal is deposited. Therefore, in order to perform both the metal gate process and the high-temperature process, such a metal gate-last process in which a metal gate is formed after a high-temperature process also needs to be employed in SGTs.
In the metal gate-last process, a polysilicon gate is formed and then a diffusion layer is formed by ion implantation. In SGTs, an upper portion of a pillar-shaped silicon layer is covered with a polysilicon gate, and thus some schemes are required.
As the width of a silicon pillar decreases, it becomes more difficult to make an impurity be present in the silicon pillar because the density of silicon is 5×1022/cm3.
In known SGTs, it has been proposed that the channel concentration is set to be a low impurity concentration of 1017 cm−3 or less and the threshold voltage is determined by changing the work function of a gate material (e.g., refer to PTL 3).
It has been disclosed that, in planar MOS transistors, the sidewall of an LDD region is formed of a polycrystalline silicon having the same conductivity type as a low-concentration layer, surface carriers of the LDD region are induced by the difference in work function, and thus the impedance of the LDD region can be reduced compared with LDD MOS transistors with an oxide film sidewall (e.g., refer to PTL 4). It has also been disclosed that the polycrystalline silicon sidewall is electrically insulated from a gate electrode. The drawings show that the polycrystalline silicon sidewall is insulated from a source and a drain by an interlayer insulating film.